CVD Coatings in Semiconductor Epitaxy: Engineering Parameters, SiC/TaC Selection and Failure Control

Author | Engineer Nickwu | Engineer, Advanced Materials Division, Vetek Semiconductor

Introduction: In epitaxy, a coated graphite susceptor is part of the reactor’s thermal, chemical and contamination boundary. Its value lies not in coating thickness alone, but in how consistently the finished part preserves wafer temperature, surface stability and repeatability through growth and cleaning cycles.

1. CVD Coating as an Epitaxy Process Boundary

Core conclusion: Even with unchanged temperature, pressure and gas flow, coating roughness, deposits, pocket geometry or interface degradation can alter heat transfer and surface chemistry. The coated susceptor should therefore be treated as a process-critical reactor component, not a passive wafer holder.

Typical growth temperatures illustrate the load: GaN MOCVD often runs near 1000–1100°C, Si epitaxy around 1050–1200°C, and SiC epitaxy roughly 1500–1700°C. Wafer temperature depends on heater power plus susceptor geometry, emissivity, pocket depth, rotation and gas flow.

Planetary MOCVD uses laminar flow and multiple carrier rotation to improve thickness, composition and doping uniformity.[1]

2. CVD SiC and TaC Coating Parameters

Core conclusion: “100 μm coating” is not a complete semiconductor specification. Density, purity, microstructure, roughness, CTE, thickness distribution, adhesion and defect control must be considered together, especially at pockets, edges, holes and shadowed features where local deposition may differ.

The engineering chain is:

CVD temperature / pressure / gas ratio → grain growth → density / roughness / stress → coating life.

Higher pressure increased roughness and porosity, while excessive temperature produced coarser structures.[3]

3. Thermal Uniformity and Run-to-Run Repeatability

Core conclusion: A coating can become process-unacceptable before it visibly peels. Thickness drift, recession, deposits or roughness change can alter wafer-to-susceptor heat transfer and emissivity, creating temperature or run-to-run drift while the component still appears mechanically intact.

Wafer heat balance:

Qtotal = Qconduction + Qradiation + Qconvection

The coated susceptor influences these terms through material properties, surface condition and geometry. Pocket depth matters because coating buildup changes the final wafer seating geometry.

A nominal 100 μm coating that varies around a pocket can change both local thermal path and final dimensions. Small variation does not automatically cause non-uniformity, but post-coating pocket depth should be a CTQ.

During production:

growth deposits + cleaning + thermal cycling → roughness/emissivity drift → thermal-boundary drift → wafer-temperature drift → growth-rate/composition drift.

Component lifetime should therefore be defined by process limits—not simply by “no visible breakage.”

4. CVD SiC vs. CVD TaC Selection

Core conclusion: CVD SiC is the practical baseline for many Si, GaN and SiC epitaxy parts because of its maturity, purity and compatibility with graphite. TaC becomes attractive when extreme temperature or Si-rich chemistry makes SiC recession the verified lifetime-limiting mechanism.

Selection Decision TreeT < ~1400°C and SiC chemically compatible?

→ Yes: qualify CVD SiC.

→ No: continue.

SiC epitaxy at ~1500–1700°C?

→ Start with proven SiC. If recession, particles or short life dominate, compare TaC.

>2000°C or severe Si-vapor exposure?

→ Prioritize TaC evaluation.

TaC is not chemically invulnerable. At 1973 K in silicon vapor, CVD TaC formed TaSi₂/SiC reaction products; increasing Si exposure increased corrosion depth and roughness.[4] Selection should therefore be based on degradation rate in the real reactor, not melting point alone.

5. CVD Coating Failure Mechanisms

Core conclusion: Most coated-susceptor failures arise from coupled thermal stress, deposition non-uniformity, chemical recession and cleaning or handling damage. Failure analysis should link the visible defect to its root mechanism and then to the wafer symptom instead of stopping at “coating peeling.”

A useful first-order thermal-stress relation is:

σ ≈ E × Δα × ΔT

where E is coating modulus, Δα the coating/substrate CTE difference and ΔT the thermal excursion. This is why graphite CTE matching matters almost as much as coating purity.

Deep pockets, holes and grooves can receive different precursor transport:

local thin/porous coating → thermal/chemical attack → graphite exposure → erosion → particles → wafer-defect risk.

A component may therefore reach process end-of-life before mechanical end-of-life.

6. Qualification and RFQ Requirements

Core conclusion: Qualification should convert reactor conditions into measurable CTQs and verify them on the finished geometry. Material certificates alone are insufficient; the target is repeatable coating integrity, dimensions and thermal/chemical behavior through representative growth and cleaning cycles.

A practical specification should include:

• Material: graphite grade, purity, CTE; coating phase and purity.
• Coating: thickness, local limits, roughness, pinhole/porosity criteria, adhesion or thermal-cycle criteria.
• Geometry: pocket depth after coating, flatness/runout, OD/ID, holes and rotation-related CTQs.
• Process: wafer size, temperature, gases, pressure, heating/rotation mode, cleaning chemistry and expected cycles.

Recommended checkpoints:

Incoming → defined growth cycles → cleaning → end-of-life.

Correlating these checkpoints with particle and wafer data is more useful than visual inspection alone.

7. FAQ

How thick should CVD SiC be?

Around 100 μm is a useful reference, not a universal optimum. Geometry, corrosion allowance, stress and dimensional tolerance determine the target.

Does thicker coating always last longer?

No. It adds corrosion reserve but may also increase residual stress and dimensional shift.

Why does SiC coating peel?

Typical contributors are CTE mismatch, residual stress, interface defects, edge geometry, thermal cycling, chemical attack and cleaning damage.

When should TaC replace SiC?

When high-temperature or Si-rich attack is proven to be the dominant SiC lifetime limit and TaC gives a better lifecycle result.

Conclusion

Core conclusion: CVD-coated graphite should be qualified as part of the epitaxy process. The target is stable thermal, chemical and dimensional behavior throughout production, with end-of-life defined by measurable process CTQs rather than visible damage alone.

The engineering chain is:

graphite substrate → CVD microstructure → finished geometry → thermal/chemical stability → wafer repeatability.

The better question is not simply “How thick is the coating?” but “How will this component behave after repeated growth, cleaning and thermal cycles, and what measurable limit defines its end of life?”

References

[1] AIXTRON SE, Planetary Principle (MOCVD).

[2] SGL Carbon, SIGRAFINE® SiC Coating – Material Data.

[3] Huo Y. et al., Scientific Reports 16, 4150 (2026), “Study of the Process-Structure-Property Correlation in CVD-SiC Coatings on Graphite Substrates.”

[4] Hao K. et al., Vacuum 241, 114677 (2025), “Silicon Vapor Induced Corrosion Mechanisms of CVD TaC Coatings on Graphite Substrates.”

Engineer Nickwu has 15 years of experience in the R&D of CVD coatings and carbon-based hot-zone materials. He led the project to introduce mass production for China's first TaC-coated graphite components used in 8-inch SiC epitaxy. He has participated in numerous hot-zone design and failure analysis projects for SiC crystal growth and holds seven invention patents related to hot-zone materials.